Today's semiconductor technology has been advancing in a direction that requires ever increasing numbers of interconnections with integrated circuits. Typically a large number of integrated circuits are formed on a silicon wafer, then are sliced into individual integrated circuit dies (or chips). Each die is then packaged and used.
Electrical connections to the dies are made in one of a few ways. In one type of package, a die-receiving area (or die receiving cavity) is provided in the package to receive an integrated circuit die. A number of conductive lines (traces or leads) whose outer ends are electrically connected to pins or leads on the package extend inward towards the die receiving area, usually in a radial pattern, stopping just short of the periphery of the die. The die has a number of "bond pads" for the purpose of making electrical connections therewith, and is mounted such that the bond pads are exposed. The inner ends of these conductive traces or leads are disposed such that they form an array of connection points surrounding the die. Very thin "bond wires" (usually gold) are then used to connect the connections points on a one-for-one basis with the bond pads on the integrated circuit die. Each bond wire has an "approach angle" to the die. After mounting, the area or cavity containing the die and the bond wires is usually sealed with a cover or an encapsulant to protect them from moisture or other physical damage.
In another type of package, commonly referred to as "TAB" (Tape Automated Bonding) packaging, a lead frame is provided in a tape format. Each lead frame has a die-receiving area, where the semiconductor die is mounted. The leads (conductive leads) in the lead frame typically approach the die-receiving area in a radial pattern, with their inner ends forming contact points to which the die will be connected. The die has a matching pattern of "bond pads". The die is mounted such that the bond pads align with and make electrical contact with the contact points of the lead frame.
Often, an integrated circuit die may be used in one of several different packages. For example, the same die may be packaged in a plastic or ceramic DIP package (dual inline package), a leadless chip carrier (LCC), a plastic leaded chip carrier (PLCC), etc.. While these packages have a die-receiving area and conductive traces in common, the arrangement of conductive traces in the die-receiving area may be slightly different from one package to another. As a result, the approach angle of a bond wire running to any given bond pad on the die from a corresponding conductive trace may vary somewhat from package to package.
As mentioned before, "conductive traces" are generally printed traces on a ceramic substrate or on a printed circuit board. "Conductive leads" are usually conductors in a lead-frame, such as in a TAB package. For the purposes of this specification, the term "conductive lines" will be used hereinafter to refer collectively to conductive leads, conductive traces, and bond wires.
FIG. 1 show a portion of a typical semiconductor device package 100 of the prior art. A die 106 is mounted in a die-receiving area 104. Around the periphery of the die-receiving area 104 is a raised surface 102 with a number of conductive traces 110. These traces are shown along one side only for illustrative clarity, but are usually disposed along all sides of the die-receiving area 104. A series of square bond pads 108 is arranged along the edges of the die. Again, FIG. 1 shows bond pads along only one edge of the die for illustrative clarity, but bond pads are usually provided along all edges of the die. Bond wires, e.g., 112a, 112b, 112c, 112d, and 112e, connect conductive traces 110 to bond pads 108 on a one-to-one basis. Note that the conductive traces approach the die 106 in a generally radial pattern (fanned-out or fanned pattern), such that the approach angles of conductive traces and bond wires closest to an end of die edge 118 (e.g., 110d, 112d, 110e, and 112e) are the furthest off-perpendicular, while the approach angles of conductive traces and bond wires nearest the center of edge 118 (e.g. 110a and 112a) are substantially perpendicular to the edge 118, with the off-perpendicular component of approach angles generally increasing with increasing distance from the center of the edge. A centrally located conductive trace 110a and bond wire 108a approach the die such that their approach angle (as shown by dashed line 114) is substantially perpendicular to the edge of die 106. Another conductive trace 110b and bond wire 112b, located three traces (and bond wires) away from the centrally located conductive trace 110a (and bond wire 112a), approaches the die 106 at an off-perpendicular angle .theta..sub.3. Yet another conductive trace 110c and bond wire 112c, located nine traces (and bond wires) away from the centrally located conductive trace 110a (and bond wire 112a), approach the die at an off-perpendicular angle .theta..sub.9 (greater than .theta..sub.3).
FIG. 2 shows a cutaway of die 106. A typical bond wire 112 is shown attached to a typical square bond pad 108. An inter-pad spacing of "d" is shown, between bond pads. The bond wire 112 comes in at an approach angle .theta.. The contact area 220 formed by the bond wire 112 with the bond pad 108 is generally elliptical. This is typical of contact footprints between bond wires and bond pads which usually have an elongated shape, with the "elongated dimension" (or "major axis" of the shape, defined hereinbelow) substantially aligned with the approach angle.
Typical prior art bond pads are square, as shown in FIGS. 1 and 2, and are capable of receiving bond wires over a wide range of approach angles, since a bond pad is typically much larger than the contact footprint formed between it and a bond wire (or conductive lead in a TAB package). Usually, there is a required minimum inter-pad spacing "d" to minimize the possibility of shorting or coupling between adjacent bond pads or bond wires.
As stated previously, however, there is a great deal of pressure in modern integrated circuit technology to provide greater numbers of interconnections (i.e., bond pads) to integrated circuit dies. Unfortunately, there is a limited amount of space along the edges of an integrated circuit die for bond pads. One possible solution is to provide multiple rows of bond pads along the edges of the die, but this would require bond wires to cross over one another, creating a serious risk of a short circuit, even if the rows of bond pads are staggered. This problem is especially serious if there is a wide range of approach angles to bond pads possible for different packages.